Cadence has deepened its strategic partnership with TSMC, delivering a complete IP, EDA, and design infrastructure workflow across N3, N2, A16, and A14 process nodes. The collaboration helps customers reduce design iterations, enhance DTCO, and speed time-to-market for AI chips.

“AI innovation requires full design-cycle solutions spanning SoC to chiplets and 3D-IC,” said Chin-Chi Teng, SVP at Cadence. TSMC’s Aveek Sarkar noted that surging AI demand and shorter cycles demand proven processes and mature IP.

Cadence offers a rich IP portfolio for TSMC N2P, including DDR5 12.8G MRDIMM, PCIe 6.0, LPDDR6/5X 14.4G, and HBM4E 16G. Artisan foundation IP is already in production on N3.

Certified EDA flows cover Innovus, Virtuoso, Spectre, Celsius, Voltus, EMX, Tempus, Quantus, and Pegasus – all certified for N2 and A16, with A14 PDK co-development underway. Integrity 3D-IC platform supports TSMC COUPE reference flow, with new silicon photonics support in Virtuoso.

Agentic AI is now embedded across Cadence tools, transforming manual steps into goal-driven execution. NVIDIA’s Tim Costa highlighted the need for accelerated computing and AI-driven methods to tackle rising chip complexity.

Enhanced Genus, Innovus, and Cerebrus tools optimize for TSMC NanoFlex Pro, while A16 Super Power Rail enables dense, high-performance designs via backside power delivery.

Arm’s Eddie Ramirez emphasized the ecosystem’s role in next-gen AI infrastructure. Positron CTO Thomas Sohmers noted that Cadence’s PCIe 6.0 SerDes IP on N3P provides a reliable, predictable tape-out path for their second-gen AI inference accelerator.

ICgoodFind: Cadence and TSMC deliver a proven, AI-infused path from IP to tape-out, accelerating next-gen AI silicon.